From 018f1f4893edbb41f65e92c7e331856a663dff48 Mon Sep 17 00:00:00 2001
From: Reese <Reesegetsemails@protonmail.com>
Date: Sat, 20 Nov 2021 23:45:39 -0700
Subject: [PATCH] work

---
 .gitignore        |  1 +
 RGPC1/compiler.py | 73 ++++++++++++++++++++++++++++++++++++++++++++++-
 RGPC1/fib.ra      |  4 +--
 RGPC1/fib.rc      |  0
 RGPC1/test.ra     |  5 ++++
 RGPC1/test.rc     |  5 ++++
 6 files changed, 85 insertions(+), 3 deletions(-)
 create mode 100644 .gitignore
 create mode 100644 RGPC1/fib.rc
 create mode 100644 RGPC1/test.ra
 create mode 100644 RGPC1/test.rc

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+
diff --git a/RGPC1/compiler.py b/RGPC1/compiler.py
index dfc3867..d574c5d 100755
--- a/RGPC1/compiler.py
+++ b/RGPC1/compiler.py
@@ -8,5 +8,76 @@ if len(sys.argv) < 2:
     print("Add arguments!")
     quit()
 
+markers = {}
+
 file = open(sys.argv[1])
-print(file.readlines()[1])
+fullfile = file.readlines()
+file.close()
+output = open(sys.argv[1].strip('.ra') + '.rc', 'w+')
+line = 1
+
+registers = {
+            #normal
+            'acc':  '01000000',
+            'a':    '00100000',
+            'b':    '01100000',
+            'c':    '00010000',
+            #special
+            'zero': '00000000',
+            'full': '00000001',
+            'dbgo': '00000010',
+            'dbgi': '00000011',
+            'pgcr': '00000100'}
+
+for i in fullfile:
+    temp = None
+    binified = None
+    line = line + 1
+
+    instruction = i.strip()
+    instruction = instruction.lower().split(' ')
+    print(instruction)
+
+    if instruction[0][0] == '!':
+        markers[instruction[0][1:].strip('\n')] = line
+        line = line - 1
+        print("marker")
+
+    elif instruction[0] == 'nul':
+        print("nul")
+        output.write('00000000\n')
+
+    elif instruction[0] == 'mov':
+        print("mov")
+        temp = '010000ab;'
+        if registers.get(instruction[1], 'fail') != 'fail':
+            temp = temp + registers.get(instruction[1]) + ';'
+            temp = temp.replace('a', '1')
+
+        else:
+            binified = bin(int(instruction[1]))[2:][::-1]
+            temp = temp + binified + ';'
+            temp = temp.replace('a', '0')
+
+
+        if registers.get(instruction[2], 'fail') != 'fail':
+            temp = temp + registers.get(instruction[2])
+            temp = temp.replace('b', '1') + '\n'
+            output.write(str(temp))
+
+        else:
+            binified = bin(int(instruction[2]))[2:][::-1]
+            temp = temp + binified
+            temp = temp.replace('b', '0') + '\n'
+            output.write(str(temp))
+
+    elif instruction[0] == 'add':
+        print("add")
+
+    else:
+        print("Error!")
+        print("Line: " + str(line))
+        #quit()
+
+
+print(markers)
diff --git a/RGPC1/fib.ra b/RGPC1/fib.ra
index 7f4fc53..056eef7 100644
--- a/RGPC1/fib.ra
+++ b/RGPC1/fib.ra
@@ -1,8 +1,8 @@
-    MOV 1 A    
+    MOV 1 A
     MOV 1 B
     MOV -100 C
     MOV A DBGO
-lop:
+!lop:
     ADD A B
     MOV A B
     MOV ACC A
diff --git a/RGPC1/fib.rc b/RGPC1/fib.rc
new file mode 100644
index 0000000..e69de29
diff --git a/RGPC1/test.ra b/RGPC1/test.ra
new file mode 100644
index 0000000..d4739c4
--- /dev/null
+++ b/RGPC1/test.ra
@@ -0,0 +1,5 @@
+NUL
+MOV 100 B
+MOV 100 100
+MOV 1 A
+MOV 5 B
diff --git a/RGPC1/test.rc b/RGPC1/test.rc
new file mode 100644
index 0000000..ac9ba48
--- /dev/null
+++ b/RGPC1/test.rc
@@ -0,0 +1,5 @@
+00000000
+01000001;0010011;01100000
+01000000;0010011;0010011
+01000001;1;00100000
+01000001;101;01100000