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documentation and compiler work

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master
Reese 3 years ago
parent c84533c2e1
commit 07d4aaa2f7
4 changed files with 167 additions and 42 deletions
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53
RGPC1/assemblyone.txt
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@ -1,4 +1,5 @@
RGPC1 technical information document
also known as the ramblings of a madman with too little coffee
Instruction layout in RAM
OPCODE A B
@ -9,7 +10,7 @@ R Indicates the value stored in A/B is a register
Opcodes:
NUL = 00000000 Nothing but faster
NOP = 001010-- Nothing!
NOP = 00101000 Nothing!
ALU = 1XXXXY--
If Y is 1 invert output
@ -63,6 +64,54 @@ Example program (Human readable + binary):
MOV ACC A 0100011;01000000;00100000
JMP 2 0110000;00000010;00000000
Programming information:
R|I = Register or number
ALU Operation usage:
Not is optional and inverts the output
ADD R|I R|I NOT
SUB R|I R|I NOT
OR R|I R|I NOT
XOR R|I R|I NOT
AND R|I R|I NOT
Jumps:
Markers are defined by doing:
!marker_name
JMP marker_name
Anything else is ignored by the compiler
JNZ R|I marker_name
JGZ R|I marker_name
JLZ R|I marker_name
JEZ R|I marker_name
MOV:
MOV will move A into B
A B
MOV R|I R|I
DBL will blink a light in the control logic
DBB will beep a beeper in the control logic
NUL will do nothing and be somewhat quick about it
NOP will do nothing but be slow about it
HLT will stop the machine
Certain instructions like:
(Parts of the instruction that can store arbitrary data)
* JMP (8b: B)
* NUL (16b: A B)
* NOP (16b: A B)
* HLT (16b: A B)
* DBL (16b: A B)
* DBB (16b: A B)
Can be used to store data some data in RAM since they dont use all 24 bits
Control bus:
Layer one:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

152
RGPC1/compiler.py
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@ -25,12 +25,37 @@ def getreg(g):
temp = temp.replace('b', '0')
return temp
def getjmp(g):
temp = g
if registers.get(instruction[1], 'fail') != 'fail':
temp = temp + registers.get(instruction[1]) + ';'
temp = temp.replace('a', '1')
else:
binified = format(int(instruction[1]), '08b')[:8].replace('-', '1')
temp = temp + binified + ';'
temp = temp.replace('a', '0')
if markers.get(instruction[2], 'fail') != 'fail':
temp = temp + format(int(markers.get(instruction[2])), '08b')
temp = temp.replace('a', '1')
else:
binified = format(int(instruction[2]), '08b')[:8].replace('-', '1')
temp = temp + binified + ';'
temp = temp.replace('a', '0')
return temp + ';'
verbose = 0
if len(sys.argv) < 2:
print("Add arguments!")
quit()
if len(sys.argv) > 2:
if sys.argv[2] == '-v' or sys.argv[2] == '--verbose':
print("Running in verbose")
verbose = 1
markers = {}
file = open(sys.argv[1])
fullfile = file.readlines()
@ -38,6 +63,7 @@ file.close()
output = open(sys.argv[1].strip('.ra') + '.out', 'w+')
line = 0
markers = {}
registers = {
#normal
'acc': '01000000',
@ -55,41 +81,47 @@ for i in fullfile:
line = line + 1
instruction = i.strip()
instruction = instruction.lower().split(' ')
print(instruction)
if verbose == 1:
print(instruction)
if instruction[0][:1] == '!':
line = line - 1
markers[instruction[0][1:].strip('\n')] = line
print("marker")
if verbose == 1:
print("marker")
if verbose == 1:
print(markers)
print(markers)
for i in fullfile:
temp = None
binified = None
line = line + 1
instruction = i.strip()
instruction = instruction.lower().split(' ')
print(instruction)
if verbose == 1:
print(instruction)
if instruction[0] == 'nul':
print("nul")
if verbose == 1:
print("nul")
output.write('00000000;00000000;00000000\n')
elif instruction[0] == 'nop':
print("nop")
if verbose == 1:
print("nop")
output.write('00101000\n')
elif instruction[0] == 'mov':
print("mov")
temp = '010000ab;'
temp = getreg(temp)
print(temp)
if verbose == 1:
print("mov")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'add':
print("add")
temp = '11000yab;'
temp = getreg(temp)
if len(instruction) > 3:
@ -97,11 +129,12 @@ for i in fullfile:
temp = temp.replace('y', '1')
else:
temp = temp.replace('y', '0')
print(temp)
if verbose == 1:
print("add")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'sub':
print("sub")
temp = '10100yab;'
temp = getreg(temp)
if len(instruction) > 3:
@ -109,11 +142,12 @@ for i in fullfile:
temp = temp.replace('y', '1')
else:
temp = temp.replace('y', '0')
print(temp)
if verbose == 1:
print("sub")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'or':
print("or")
temp = '11100yab;'
temp = getreg(temp)
if len(instruction) > 3:
@ -121,11 +155,12 @@ for i in fullfile:
temp = temp.replace('y', '1')
else:
temp = temp.replace('y', '0')
print(temp)
if verbose == 1:
print("or")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'xor':
print("xor")
temp = '10010yab;'
temp = getreg(temp)
if len(instruction) > 3:
@ -133,11 +168,12 @@ for i in fullfile:
temp = temp.replace('y', '1')
else:
temp = temp.replace('y', '0')
print(temp)
if verbose == 1:
print("xor")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'and':
print("and")
temp = '11010yab;'
temp = getreg(temp)
if len(instruction) > 3:
@ -145,11 +181,12 @@ for i in fullfile:
temp = temp.replace('y', '1')
else:
temp = temp.replace('y', '0')
print(temp)
if verbose == 1:
print("and")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'jmp':
print("jmp")
temp = '011000a0;'
if markers.get(instruction[1], 'fail') != 'fail':
temp = temp + format(int(markers.get(instruction[1])), '08b')
@ -160,45 +197,84 @@ for i in fullfile:
temp = temp + binified + ';'
temp = temp.replace('a', '0')
temp = temp + ';00000000;'
print(temp)
output.write(temp+ '\n')
if verbose == 1:
print("jmp")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'jnz':
temp = '000100a0;'
temp = getjmp(temp)
if verbose == 1:
print("jnz")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'jgz':
temp = '010100a0;'
temp = getjmp(temp)
if verbose == 1:
print("jgz")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'jlz':
temp = '001100a0;'
temp = getjmp(temp)
if verbose == 1:
print("jlz")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'jez':
temp = '011100a0;'
temp = getjmp(temp)
if verbose == 1:
print("jez")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'dbl':
print("dbl")
temp = '00001000;00000000;00000000;'
print(temp)
if verbose == 1:
print("dbl")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'dbb':
print("dbb")
temp = '01001000;00000000;00000000;'
print(temp)
if verbose == 1:
print("dbb")
print(temp)
output.write(temp + '\n')
elif instruction[0] == 'hlt':
print("hlt")
temp = '00000100;00000000;00000000;'
print(temp)
if verbose == 1:
print("hlt")
print(temp)
output.write(temp + '\n')
elif instruction[0] == '':
print("newline")
temp = '00000000;00000000;00000000;'
print(temp)
if verbose == 1:
print("newline")
print(temp)
output.write(temp + '\n')
elif instruction[0][:1] == '!':
print("marker")
print("Ignoreing this")
if verbose == 1:
print("marker")
print("Ignoring this")
line = line - 1
pass
else:
print("Error!")
print("Line: " + str(line))
#quit()
print("Content: " + i)
quit()
print(markers)
output.close()
print("All done!")
print("Data written to: " + sys.argv[1].strip('.ra') + '.out')

2
RGPC1/fib.out
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@ -4,4 +4,4 @@
11000011;00100000;01100000;
01000011;00100000;01100000;
01000011;01000000;00100000;
01100010;00000010;00000000;
00110010;01000000;00000010;

2
RGPC1/fib.ra
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@ -5,4 +5,4 @@ MOV A DBGO
ADD A B
MOV A B
MOV ACC A
JMP loop
JLZ ACC loop

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