From 3e31d73b6818d3fe57145ef32fca093f06d95d22 Mon Sep 17 00:00:00 2001 From: Reese Date: Mon, 16 May 2022 13:38:23 -0600 Subject: [PATCH] Hello yes I am reworking the RGPC3 --- RGPC2/assemblytwo.txt | 1 - RGPC2/test.txt | 3 + RGPC3/assemblythree.txt | 119 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+), 1 deletion(-) create mode 100644 RGPC2/test.txt create mode 100644 RGPC3/assemblythree.txt diff --git a/RGPC2/assemblytwo.txt b/RGPC2/assemblytwo.txt index 3c8808c..e315b80 100644 --- a/RGPC2/assemblytwo.txt +++ b/RGPC2/assemblytwo.txt @@ -53,7 +53,6 @@ Instruction set: X1XX = Zero 1XXX = Not zero - Pseudo instructions: MOV = OR {Destination} {Source} ZERO HLT = ( diff --git a/RGPC2/test.txt b/RGPC2/test.txt new file mode 100644 index 0000000..6912d48 --- /dev/null +++ b/RGPC2/test.txt @@ -0,0 +1,3 @@ +0110;0000;1 +0110;0000;110110 +0010;0000;0001;0010;0000;0000 diff --git a/RGPC3/assemblythree.txt b/RGPC3/assemblythree.txt new file mode 100644 index 0000000..e0903f8 --- /dev/null +++ b/RGPC3/assemblythree.txt @@ -0,0 +1,119 @@ +RGPC3 technical information document / programmers guide + +16 bits wide + +Concept one: + + Instruction format: + 1: + OPCO OUTR AREG BREG JFLG + XXXXX;XXXXX;XXXXX;XXXXX;XXXX;XX + 2: + OPCO OUTR IMMEDIATE + XXXXX;XXXXX;XXXXX:XXXXX:XXXX;XX + + 3: + OPCO OUTR AREG SHFT D + XXXXX;XXXXX;XXXX;XXXX;X;XXXX;XX + + OPCO = Opcode + OUTR = Output Register + AREG = A Register + BREG = B Register + JFLG = Jump Flags + SHFT = Shift amount + D = Shift direction 0 for right 1 for left + + If running LDI use 2 + If running SHF use 3 + + Registers: + ZERO = 00000 R 16Bit + G1 = 00001 R/W 16Bit + G2 = 00010 R/W 16Bit + G3 = 00011 R/W 16Bit + G4 = 00100 R/W 16Bit + OUTP = 00101 W 16Bit + PGCR = 00110 R/W 16Bit + G5 = 00111 R/W 16Bit + G6 = 01000 R/W 16Bit + GPIO1 = 01001 R/W 16Bit + GPIO2 = 01010 R/W 16Bit + GPIO3 = 01011 R/W 16Bit + GPIO4 = 01100 R/W 16Bit + G7 = 01101 R/W 16Bit + G8 = 01110 R/W 16Bit + RAND = 01111 R 16Bit + SPTR = 10000 R/W 16Bit + SLOC = 10001 R/W 16Bit + MPTR = 10011 R/W 16Bit + + Instruction set: + If Y = 1 invert ALU output + OR = 0Y001 + ADD = 0Y010 + SUB = 0Y011 + AND = 0Y100 + XOR = 0Y101 + LDI = 0Y110 + JMP = 0Y111 + Jump flags: + XXX1 = Greater than zero + XX1X = Less than zero + X1XX = Zero + 1XXX = Not zero + PSH = 1Y001 + POP = 1Y010 + STR = 1Y011 + LOD = 1Y100 + SHF = 1Y101 + + Pseudo instructions: + MOV = OR {Destination} {Source} ZERO + HLT = { + MOV PGCR G1 + JMP G1 + } + JGZ = JMP JFLG:0001 + JLZ = JMP JFLG:0010 + JIZ = JMP JFLG:0100 + JNZ = JMP JFLG:1000 + JMP = JMP JFLG:1111 + + Programmers guide: + TODO: + + + +Concept two: + + 16Bit wide + 15Bit addressing 1 bit for RAM select + program in RAM + + Opcode ARGS + XXXX;XXXX;XXXX;ABXX:... any number of words + + If A|B = 1 then A|B will be treated as an immediate VALUE + + R|I|M = Register OR Immediate OR Memory + + Opcodes: + MOV = 0000;0000;0000;A000 MOV A > B + ADD = 0000;0000;0001;ABY0 A + B > ACC : If Y = 1 invert output + SUB = 0000;0000;0010;ABY0 A - B > ACC : If Y = 1 invert output + OR = 0000;0000;0011;ABY0 A | B > ACC : If Y = 1 invert output + XOR = 0000;0000;0100;ABY0 A ^ B > ACC : If Y = 1 invert output + AND = 0000;0000;0101;ABY0 A & B > ACC : If Y = 1 invert output + SHF = 0000;0000;0110;ABYL A <> B > ACC : If Y = 1 invert output : If L = 1 shift left + + JMP = 0000;0000;0111;A000 JMP to A + JEZ = 0000;0000;1000;AB00 JMP to B if A == 0 + JNZ = 0000;0000;1001;AB00 JMP to B if A != 0 + JGZ = 0000;0000;1010;AB00 JMP to B if A > 0 + JLZ = 0000;0000;1011;AB00 JMP to B if A < 0 + + PSH = 0000;0000;1100;A000 PSH A to the stack + POP = 0000;0000;1101;0000 POP item from stack and put into R|M + +