i did some stuff with the RGPC2 compiler still unfinished

RGPC2/assembler.py

@@ -1,9 +1,25 @@
 #!/bin/env python3
-
 import sys
 
-verbose = False
+def get_oreg(inst, regarg):
+        inst = inst.replace("outr", registers.get(regarg, '0000'))
+        return inst
+
+def get_areg(inst, regarg):
+    inst = inst.replace("areg", registers.get(regarg, '0000'))
+    return inst
+
+def get_breg(inst, regarg):
+    inst = inst.replace("breg", registers.get(regarg, '0000'))
+    return inst
 
+def replace_args313(instout):
+    instout = get_oreg(instout, instruction[3])
+    instout = get_areg(instout, instruction[1])
+    instout = get_breg(instout, instruction[2])
+    return instout
+
+verbose = False
 if len(sys.argv) < 2:
     print("Add arguments!")
     quit()
@@ -17,8 +33,6 @@ fullfile = file.readlines()
 file.close()
 output = open(sys.argv[1].replace('.rasm', '.out'), 'w')
 
-line = 0
-
 markers = {}
 registers = {
             'zero':  '0000',
@@ -40,8 +54,7 @@ registers = {
             }
 
 print("Finding markers")
-
-
+line = 0
 for i in fullfile:
     line = line + 1
     instruction = i.strip()
@@ -65,6 +78,7 @@ line = 0
 for i in fullfile:
     temp = None
     instout = None
+    binified = None
     line = line + 1
     instruction = i.strip()
     instruction = instruction.lower().split(' ')
@@ -72,15 +86,104 @@ for i in fullfile:
     if verbose == True:
         print(instruction)
 
-    if instruction[0] == 'ldi':
+    if instruction[0] == '' or instruction[0][0] == "#" or instruction[0][0] == "!":
+        if verbose == True:
+            print(instruction)
+        pass
+
+    elif instruction[0] == 'ldi':
         instout = "0110;outr;binified\n"
-        instout = instout.replace("outr", registers.get(instruction[2], '0000'))
-        binified = format(int(instruction[1]), '016b')[:16].replace('-', '1')
+        instout = get_oreg(instout, instruction[2])
+        binified = format(int(instruction[1]) & 0xffff, 'b')
         instout = instout.replace("binified", binified)
         if verbose == True:
             print(instout)
         output.write(instout)
+
+    elif instruction[0] == 'add':
+        instout = "0010;outr;areg;breg;0000;0000\n"
+        instout = replace_args313(instout)
+        if verbose == True:
+            print(instout)
+        output.write(instout)
+      
+    elif instruction[0] == 'sub':
+        instout = "0011;outr;areg;breg;0000;0000\n"
+        instout = replace_args313(instout)
+        if verbose == True:
+            print(instout)
+        output.write(instout)
+
+    elif instruction[0] == 'mov':
+        instout = "0001;outr;areg;0000;0000;0000\n"
+        instout = get_oreg(instout, instruction[2])
+        instout = get_areg(instout, instruction[1])
+        if verbose == True:
+            print(instout)
+        output.write(instout)
+      
+    elif instruction[0] == 'or':
+        instout = "0001;outr;areg;breg;0000;0000\n"
+        instout = replace_args313(instout)
+        if verbose == True:
+            print(instout)
+        output.write(instout)
+    
+    elif instruction[0] == 'nor':
+        instout = "1001;outr;areg;breg;0000;0000\n"
+        instout = replace_args313(instout)
+        if verbose == True:
+            print(instout)
+        output.write(instout)
+    
+    elif instruction[0] == 'and':
+        instout = "0100;outr;areg;breg;0000;0000\n"
+        instout = replace_args313(instout)
+        if verbose == True:
+            print(instout)
+        output.write(instout)
+    
+    elif instruction[0] == 'nand':
+        instout = "1100;outr;areg;breg;0000;0000\n"
+        instout = replace_args313(instout)
+        if verbose == True:
+            print(instout)
+        output.write(instout)
+    
+    elif instruction[0] == 'xor':
+        instout = "0101;outr;areg;breg;0000;0000\n"
+        instout = replace_args313(instout)
+        if verbose == True:
+            print(instout)
+        output.write(instout)
+    
+    elif instruction[0] == 'xnor':
+        instout = "1101;outr;areg;breg;0000;0000\n"
+        instout = replace_args312(instout)
+        if verbose == True:
+            print(instout)
+        output.write(instout)
+
+    elif instruction[0] == 'jmp':
+        if markers.get(instruction[1], "0") != "0":
+            instout = "0110;0110;binified;0000;0000;0000\n"
+            binified = format(int(markers.get(instruction[1])) & 0xffff, 'b')
+            instout = instout.replace("binified", binified)
+            if verbose == True:
+                print(instout)
+            output.write(instout)
+        else:
+            print("Not added yet! you can only unconditionally jump to markers")
+
+    else:
+        print("Error! on line: " + str(line))
+        print(instruction)
+        if verbose != True:
+            exit(1)
+
+# TODO Make the compiler do conditional jumps and jumps with immediate values
+# also make sure the user knows you must let the compiler use a register for conditional jumps
         
-        # TODO: make it work i guess i dunno
 
 output.close()
+print("Done!")

RGPC2/fib.out

@@ -1,2 +1,6 @@
-0110;0001;1000000000000001
-0110;0010;0000000000000001
+0110;0001;1
+0110;0010;1
+0010;0011;0001;0010;0000;0000
+0001;0010;0001;0000;0000;0000
+0001;0001;0011;0000;0000;0000
+0110;0110;100;0000;0000;0000

RGPC2/fib.rasm

@@ -1,6 +1,10 @@
-ldi -1 g1
+ldi 1 g1
 ldi 1 g2
+
+
 !loop
+
+
 add g1 g2 g3
 mov g1 g2
 mov g3 g1